High Performance Computing (HPC) platforms may be frequency constrained, e.g., due to the need for accommodating a large number of cores and for example an equal number of VPUs (Vector Processing Units) to meet the performance requirements within a fixed power budget. Due to the large number of cores, some processors within some platforms are designed to be operating at less than 2 GHz. This is a significantly lower frequency compared to current and next generation of server processor cores (e.g., at 3.2+ GHz). Lower frequency adds more pressure on the ring (formed by the cores and processing units), as the ring throughput is generally proportional to the frequency.
Thus, HPC platforms may require a large amount of memory bandwidth per socket in-order to keep the byte/flop ratio at a high level.